PDKMaster circuits and layouts for bandgap and ADC

Posted on ma 03 oktober 2022 in NLnet • Tagged with AnaMS

After a first pure report on analog blocks scalability, I am happy to be able to report on the first PDKMaster based circuits and layouts for the NGI Zero PET funded Analog/Mixed-Signal Library project in this blog post. Reports on the scalability of a bandgap and an ADC circuits …

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Two More Reports on Scalable Analog blocks

Posted on vr 30 september 2022 in NLnet • Tagged with AnaMS

The first results for the NGI Zero PET funded Analog/Mixed-Signal Library project were already presented in a previous blog post. Now the scalability reports on the rest of the analog blocks have been made available by LIP6; one for a DAC and one for a PLL.


A comparison …

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PDKMaster v0.2.0 and Demo Packages on Pypi

Posted on wo 24 augustus 2022 in NLnet • Tagged with AnaMS

PDKMaster v0.2.0

In previous post on first results for analog/mixed-signal I already mentioned I would update on the status of PDKMaster development. This has taken me a few weeks more than planned but here it is.

One of the targets in the NGI Zero PET funded Analog …

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First Analog/Mixed Signal Project Results

Posted on wo 15 juni 2022 in NLnet • Tagged with AnaMS

In a previous professional life I have been working on radiation hardened SRAM compiler design amongst other things. There I used Cadence Virtuoso for analog circuit development. It is one of the proprietary reference analog design platforms. As a hobby I was also doing open source software development enjoying the …

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NLnet018TV Measurement Report

Posted on wo 19 mei 2021 in NLnet

Almost a year ago I reported on the NLnet018TV test chip design for my NLnet project. I did have verification measurements of the chip available now for several weeks but because of the Libre-SOC prototype tape-out taking all of my time I did not find time and motivation to summarize …

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PDKMaster v0.1 release and FreePDK45 example

Posted on ma 15 maart 2021 in NLnet

After a lot of blood, sweat and tears I have now reached a new milestone for my NGI0 NLnet project. I released v0.1 of the PDKMaster python framework together with a standard cell library generator and an example PDK implementation for the FreePDK45 technology. It consist of the following …

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Poor Men's SMU, part 4: Calibration

Posted on do 11 februari 2021 in NLnet • Tagged with PM-SMU

As reported in my previous blog on using the AD5522 SMU development board it was mentioned calibration would be needed to get more accurate low-voltage and low-current measurements.


An important aspect of doing calibration is the order in which the parameters are calibrated and what references are used during …

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Poor Men's SMU, part 3: Diodes are Forever

Posted on zo 17 januari 2021 in NLnet • Tagged with PM-SMU

This is third part on my adventures with the AD5522 SMU development board. For history you can look at part 1 and part 2.

After getting the SMU working and being able to operate it from Jupyter notebooks on a raspberry Pi I now decided to use the device to …

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Poor Men's SMU, part 2

Posted on za 09 januari 2021 in NLnet • Tagged with PM-SMU

This is a continuation of my adventure with the AD5522 development board (see part 1 ). I did make progress on setting it up but as always it has taken much more time than wanted to debug the setup.

Schrödinger's cat

One problem I had to solve was that the setup …

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Poor Men's Source Measurement Unit (SMU)

Posted on zo 03 januari 2021 in NLnet • Tagged with PM-SMU


In my previous professional life doing semiconductor process development I used so called source measure units (SMUs) for measuring out transistors. Although I don't remember the exact type number, I guess I had access to a HP 4145A semiconductor parametric analyzer.

Nice thing about these units is that these …

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Fixing the ESD generator

Posted on zo 01 november 2020 in NLnet

This is a continuation on my previous blog on first tests on the ESD generator.


After some more debugging the voltage multiplier of the ESD Generator has been made to work. Detailed simulation results of the problems can be found in this Jupyter notebook in the created sim folder …

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First testing of and changes to ESD generator

Posted on zo 04 oktober 2020 in NLnet

As reported in a previous blog post I am working on a small circuit to generate high voltages for some ESD testing. I now received the PCBs and the components for on the PCB and even did find some time to do the first testing of the design. As a …

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ESD Generator: high voltage generator for ESD testing

Posted on zo 12 juli 2020 in NLnet

After tape-out of NLNet018TV I am now working on implementing the test procedures and gathering the equipment needed for executing the tests.

For ESD testing high voltages with limited charges need to be generated. This high voltage charge is then applied over two pins on the test chip to see …

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NLNet018TV: a fully automated test chip design

Posted on za 13 juni 2020 in NLnet

I am working on a NGI0 NLnet funded project and I now did reach a first milestone in the project. I did tape-out a test chip which kept me busy for the last two months and is also the reason I neglected this blog the last months. The milestone is …

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