Almost a year ago I reported on the NLnet018TV test chip design for my NLnet project. I did have verification measurements of the chip available now for several weeks but because of the Libre-SOC prototype tape-out taking all of my time I did not find time and motivation to summarize the measurements for this blog up to now.
For this PGA package a PCB adapter board was designed to make it easier to connect to the different pins. The KiCad design files of the PCB can be found here. For production of the PCBs I used JLCPCB. Below you find the picture of the PCB on the left and on the right the PCB with the chip and headers soldered on and pins connected for measurement:
The full report of the actual measurement can be found here; original notebook and saved data can be retrieved from the snowwhite repository. The notebook is called NLNet018TV_meas.ipynb and the measured data NLNet018TV.npz. In the rest of the blog a summary of the measurements will be given. The main message is that no showstoppers were discovered for the Libre-SOC prototype tape-out; IO and SRAM cell are working fine.
Functionality of SR latches has been succesfully verified and drive strength measured. More details are in the measurement report.
- The logic cell and IO themselves were succesfully powered by the designed IO cells
- For same designed drive strength the source current was relatively higher than the sink current (plot is below). For the prototpye the design is slightly adapted to bring them closer together.
- For the input the switching threshold is around 0.92V; this is still acceptable as it is higher than the 0.8V Vil of TTL and LVCMOS but ideally this would be closer to the 1.5V Vt of TTL and LVCMOS.
IO drive strength plot (pu=pull-up, pd=pull-down); left all curves, right zoom in on pull-up/pull-down functionality drive strength:
The plots are clipped around 22µA due to measurement limits imposed by the AD5522 SMU.
- The measured hold static noise margin (SNM) is around 600mV (plot below). This metric is a measuremnt for the SRAM robustness but detailed explanation goes too far for this blog. The measured value is very satisfactory as a value of 200-300mV would still be acceptable.
- Due to a design mistake read SNM could not be measured but write-trip point measurement still show robustness of the cell when word line is open and both bitlines are forced high.
- A write-trip point of around 0.80 V was measuremed (plot below); this is also a good value as there is enough margin to both ground and supply voltage.
SRAM plots, left hold SNM, right WTP.