PDKMaster v0.1 release and FreePDK45 example

Posted on ma 15 maart 2021 in NLnet

After a lot of blood, sweat and tears I have now reached a new milestone for my NGI0 NLnet project. I released v0.1 of the PDKMaster python framework together with a standard cell library generator and an example PDK implementation for the FreePDK45 technology. It consist of the following three releases:

  • PDKMaster v0.1 (PyPI)

    PDK Master is a tool to manage PDKs for ASIC design and a framework for designing circuits and layouts in those technologies. It consists of different parts:

    • Python classes to descibe the primitives of a technology like the process layers use in a design and the devices that can be made in the technology. The definition of the technology also contains the design rules that need to be obeyed so this all can be derived
    • Python classes to represent circuit and layouts using these primitives and conforming to their design rules. Focus is on easy parameterized circuit design and layout with effortless scalability between technologies.
    • Export functions to generate the setup files for other tools, currently Coriolis P&R and klayout design viewer/editor.
    • Simulation interface so circuits defined in PDKMaster can be simulated.
  • c4m-flexcell v0.0.4 (PyPI)

    This is a scalable standard cell library used to generate the standard cells that are part of the FreePDK45 PDKMaster release but also used for the tape-out of the libre-SOC 0.18um prototype using a NDAed PDK.

  • c4m-pdk-freepdk45 v0.0.1 (PyPI), tarball

    This has two different release forms, one on PyPI with only the PDKMaster based FreePDK45 PDK and a more complete tarball that contains also the exported files:

    • The python module source code, the FreePDK45 technology description is mainly one python file from which everything else is generated.
    • Generated support files for Coriolis P&R and KLayout FreePDK45 viewing editing
    • The c4m-flexcell generated FlexLib standard cell library with gds, spice, verilog, VHDL and liberty file views.
    • Example flow to synthesize and place-and-route Arlet's 6502 core using Coriolis.
    • Example python notebook showing PDKMaster's ability to combine parametric design and layout in one file. The example is the design of a minimum area balanced inverter.

More details can be found in each of the links of the release. This work is under heavy development and unfortunately not much more documentation is available other than the linked to README files. Also the API is currently highly unstable with every new commit likely breaking current code. If that doesn't stop you don't hesitate to contact me on one of the links on the left or on the gitter Chips4Makers community page.