After tape-out of NLNet018TV I am now working on implementing the test procedures and gathering the equipment needed for executing the tests.
For ESD testing high voltages with limited charges need to be generated. This high voltage charge is then applied over two pins on the test chip to see if the chip survives the event. This event mimics what happens when a charged person touches a chip.
Standards exist for performing ESD tests together with expensive equipment that allows to perform the test according to the standard. For our project we do want to perform tests that also tests ESD performance but on a lower budget without claiming ESD standard performance compliance.
A first version the schema of a circuit to generate high voltages up to 4kV has been designed and is given in the next picture.
As I am not a very experienced PCB designer with even less experience with high voltages I am sure there is much room for improvement. So don't hesitate to mail me your comments or head over to the gitter page for a chat (links on the left).