NLNet018TV: a fully automated test chip design

Posted on za 13 juni 2020 in NLNet

I am working on a NGI0 NLNet funded project and I now did reach a first milestone in the project. I did tape-out a test chip which kept me busy for the last two months and is also the reason I neglected this blog the last months. The milestone is a step to the tape-out of a prototype of the libre-SOC project in the fourth quarter of this year.

Description and source code

In good open source fashion I did put all the source code in the NLNet018 TV tag on my SnowWhite git repository in the designs/NLNet018TV directory. This test chip contains some test structures to test IO pads, SR latches and an SRAM cell. In the readme file in the repostory you find a more description on the contents of the test chip.

There is one caveat though. As the design rules are given under NDA they can't be distributed. So these are located in a private directory that unfortunately can't be shared publicly. As a consequence one needs to replicate all these files before being able to regenerate the design. This makes my open source hart bleed and is also one of the reasons I am also working on my PDKMaster project (also NLNet funded) with which I am trying to make handling of the foundry NDA PDK data as open as possible.

The A in EDA

EDA stand for electronic design automation and the term is normally used for the group of software tools for desiging PCBs and ASICs. Although for digital circuits there is a high degree of automation this is not the case for tasks where layout is involved. Both for desiging PCBs as for designing analog circuits on ASICs the flow is that of doing schematic capture of the design followed by a mostly manual layout task.

For this test chip I focused on getting the automation part also in the layout part of the design. The final GDSII file, except for the logo, is fully generated by python scripts, including the dummy fill of the open area and the bonding diagram for packaging. It uses Coriolis and klayout through their respective python interfaces to achieve this. klayout is also used for DRC.

Jupyter Notebooks

During this process I also started to experiment with Jupyter Notebooks in a Jupyter Lab environment. And I like so far what I have seen, I will certainly continue looking at it further. Admittedly, due to time pressure, the IOPad notebook for generating the IO and SR latches test structures chip has grown too bulky without proper documentation. I do see it as personal shortcoming though and not one of the Python Notebook format. And before working further on higher level generation code I am planning to work on lower level building blocks to make it possible to generate design rule compliant layouts with less code and less trial-and-error.

I also used Python Notebooks using ipywidgets to design the SRAM cells and IO drivers. I first need to look further into making these public without giving away NDA data. Certainly for such design tasks I see big potential for Python Notebooks due to the access to all the scientific python tools like SciPy and others without needing to convince a proprierary EDA tool vendor to implement a custom (proprietary) flow for you needs.

Portability

This test chip is done for the TSMC 0.18µm technology which is different than the TSMC 0.35µm process that will be used for the Chips4Makers beta run. Everything developed here is done with easy portability in mind. This means that most of the work in this project on standard cells, IO and SRAM is also meant to advance the fully open source 0.35µm process further and will be reused for the Chips4Makers beta run.

As said earlier this project did show though that first more work is needed on providing lower level support for generating design rule compliant layouts before focusing further on the higher level stuff.

Next step

As is in the name, the purpose of a test chip is to test it after it is delivered. In the repository already the test plan is avalaible. So the next step is to define how these measurements will be carried out and then execute the tests once the dies arrive. The latter is expected in 3 months from now.

Especially generating the few kV voltages and applying it to the chip for ESD testing will be a challenge to me. So if you have a comment or ideas on this or anything else related to this project don't hesitate to contact me with any of the contact links on the left.