It has been some time that I posted here and it's one of my New Year Resolutions to be more active here. As reported in a presentation @ ORConf 2019 development of the Chips4Makers low volume ASIC manufacturing process is going on. Plan for this year is to do a beta run where other people can join.
In the ORConf presentation test chip tape-outs were presented. One of the test tape-outs contained a MOS6502 core and another a Z80 core. These cores are coming from FPGA implementations of old computers like a ZX Spectrum or a Commodore 64. VHDL was used to write these cores. For the top cell and the JTAG interface nMigen is used which generates Yosys RTLIL or verilog as output. So for simulation and synthesis one need to mix different RTL languages.
Open source mixed RTL synthesis
The Yosys open source synthesis tool chain has traditionally been focused on Verilog. So for make the Chips4Makers test chips a proprietary Verific plugin for the Symbiotic EDA tool suite was used to do the synthesis on the VHDL code. Luckily Tristan Gingold is working very hard on changing this story. If you look at the recent commits on the ghdl repository and the ghdlsynth-beta repository you can see a lot of VHDL synthesis related commits for GHDL and accompanying Yosys plugin.
The Yosys ghdlsynth plugin is now able to synthesize both the Z80 and MOS6502 VHDL core used for the test chips. This way I could redo the synthesis and the place-and-route for the test chip using only open source tools. In commit 77f33ae on the Retro_uC repo the synthesis for the two test chips was switched to ghdlsynth-beta.
Repeating the work
If you want to repeat this you will need the latest version of quite some software and RTL code with some non-trivial compiling and python code installation. Best to contact me or head over to the Chips4Makers Lobby on gitter.
After checking out the Retro-uC repository you have to go into asic/C4M035/SnowWhiteIII_MOS6502 or asic/C4M035/SnowWhiteIII_Z80 directory and execute make gdsii there to do the generation of the RTL code with nMigen, synthesis with Yosys and place-and-route with QFlow.
You will need recent versions of several dependencies installed for this to work out:
- yosys: synthesis software.
- ghdl: VHDL simulation and synthesis.
- ghdlsynth-beta: GHDL synthesis plugin for Yosys.
- nMigen: python hardware generation framework.
- t65: the MOS6502 VHDL core with a nMigen wrapper.
- t80: the Z80 VHDL core with a nMigen wrapper.
- c4m-jtag: reusable JTAG interface.
- QFlow: RTL-2-GDSII flow; use version 1.4, with 1.3 you will need to use lower initial density settings.
Currently I am still using the free but proprietary ModelSim for Altera FPGAs to do simulation. So the next step to take is to have a mixed RTL simulation flow using only open source tools.